Many modem data processing systems employ more than one processor core to run program applications. Such multi-core systems require mechanisms by which processor cores can communicate data with each other and determine when data sent from a source processor core to one or more destination processor cores has been received at its intended destination(s).
It is known in dual-core data processing systems for a destination processor core to transmit an acknowledgement signal on receipt of message data from a source processor core, the acknowledgement signal being transmitted directly from source core to destination core across a communication bus.
However, this message acknowledgement mechanism presents a problem in the case of a message that is directed from a source core to two or more destination cores (i.e. a multi-cast message). For multi-cast messages, before the source processor core can determine a pending message communication to be complete, the message must have been received by each of the two or more destination cores. In such systems there is a problem whereby a destination core cannot guarantee that it is the final core to clear a message notification signal and to then send back an acknowledgement signal to the source processor core without resorting to locked transfers.